A programmable logic switch is a device that controls switching on and off of a logic switch (such as a transistor) in accordance with data held in a memory. Normally, such programmable logic switches are used in an FPGA (Field Programmable Gate Array) that requires reconfigurations of logic circuits and a wiring board.
In a programmable logic switch used in an FPGA, a volatile memory such as an SRAM is used as the memory. Therefore, once the power supply is switched off, the data stored in the SRAM is erased, resulting in the need to re-read data from a separately-prepared memory region when the power supply is again switched on. Also, an SRAM is normally formed by six transistors. Therefore, in an FPGA using a large number of SRAMs, the proportion of the area occupied by the SRAMs in the FPGA chip is large. As a result, the chip area of the FPGA becomes large.
A nonvolatile programmable logic switch based on a conventional semiconductor process with high reliability has been suggested (see United States Patent Publication No. 2002/0190749, for example). In the logic switch according to United States Patent Publication No. 2002/0190749, a cell transistor that is to be a memory cell and has a floating gate is used as a pass transistor. Since data is stored in the pass transistor, the occupied area is extremely small. However, if such logic switches are incorporated into a reconfigurable circuit such as an FPGA, various kinds of problems arise due to the circuit design. For example, to use a memory cell to store data, data writing and erasing need to be performed on the cell transistor. Particularly, in an erasing operation, a high voltage is applied to the diffusion layer to be the source or the drain of the cell transistor at the time of data erasing, and the high voltage for data erasing is applied directly to the gate electrode of the transistor of the later stage. Therefore, according to United States Patent Publication No. 2002/0190749, the gate insulating film of the transistor of the later stage is made as thick as 100 to 200 nm, to prevent breaking of the transistor of the later stage.
A logic switch having memory cells and a pass transistor formed independently of each other has also been known (see U.S. Pat. No. 7,430,137, for example). In the logic switch according to U.S. Pat. No. 7,430,137, first through fourth memory cells are connected in series in this order, and the gate of the pass transistor is electrically connected to the common connection node between the second and third memory cells. In that case, the gate potential of the pass transistor is controlled by the data stored in the first and fourth memory cells, and the voltage input to each of the control gates of the first and fourth memory cells.
JP-A 7-183385 (KOKAI) discloses yet another example of a logic switch. In the logic switch according to JP-A 7-183385 (KOKAI), a resistive element and a cell transistor having a floating gate are connected in series, and the gate of a pass transistor is electrically connected to the common connection node between the resistive element and the cell transistor. The potential of the common connection node is determined by the channel resistance that varies with the data written in the memory cell, and the ratio of the potential to the resistance of the resistive element.
As will be described later, the above-mentioned United States Patent Publication No. 2002/0190749, U.S. Pat. No. 7,430,137, and JP-A 7-183385 (KOKAI) have the following problems, which were first recognized by the inventors.
According to United States Patent Publication No. 2002/0190749, the gate insulating film is thick. Therefore, to prevent short channel effects, the gate length of the transistor needs to be made larger. As a result, large-size devices need to be used, and the response speed of the entire reconfigurable circuit becomes lower. According to U.S. Pat. No. 7,430,137, at least four memory cells need to be used, and the effect to reduce the area becomes very small. According to JP-A 7-183385 (KOKAI), it is difficult to form a highly-reliable resistive element in a small area, and efficient data erasing cannot be performed.